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Instruction set architectures
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#	Item
891	Application Note AN_226 FT313H Programming Guide Document Reference No.: FT_000764 Version 1.1 Issue Date: [removed] Add to Reading List Source URL: www.ftdichip.com Language: English - Date: 2012-11-12 19:30:11 Microcontrollers USB Instruction set architectures Universal Serial Bus Host controller interface USB flash drive Processor register EXtensible Host Controller Interface PIC microcontroller Computer hardware Computer architecture Computing
892	Efficient Deterministic Multithreading through Schedule Relaxation Heming Cui, Jingyue Wu, John Gallagher, Huayang Guo, Junfeng Yang {heming, jingyue, jmg, huayang, junfeng}@cs.columbia.edu Department of Computer Science Add to Reading List Source URL: www.cs.columbia.edu Language: English - Date: 2011-12-05 14:08:53 Parallel computing Program analysis Threads Instruction set architectures Concurrent computing Program slicing Multithreading LLVM Context switch Computing Computer programming Computer architecture
893	Technical Support Document: [removed]Models and Computer Codes Add to Reading List Source URL: epa.gov Language: English - Date: 2006-03-29 14:14:49 Procedural programming languages Cluster computing OpenVMS Validation Software development process Requirement Compaq DEC Alpha Configuration management Computing Technical communication Instruction set architectures
894	Preface This book is an outgrowth of the notes and experiments developed for the graduate classes at the University of Florida. It is intended for students, hobbyists, engineers, and scientists who would like to learn ab Add to Reading List Source URL: www.rigelcorp.com Language: English - Date: 2006-07-13 13:21:19 Central processing unit Microcontrollers Assembly languages Instruction set architectures Intel MCS-51 Memory address Addressing mode Processor register Accumulator Computer architecture Computer hardware Computer engineering
895	A Bit Naming Convention for Cryptographic Algorithms Markus G. Kuhn? University of Cambridge, Computer Laboratory, New Museums Site, Pembroke Street, Cambridge CB2 3QG, United Kingdom [removed] Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 1999-04-15 16:04:36 Advanced Encryption Standard Computer memory Data transmission Endianness Metaphors Bit array X86 Word PowerPC Computer architecture Computing Instruction set architectures
896	Where’s the FEEB? The Effectiveness of Instruction Set Randomization Ana Nora Sovarel David Evans Nathanael Paul University of Virginia, Department of Computer Science Add to Reading List Source URL: www.csiir.ornl.gov Language: English - Date: 2010-03-31 18:05:52 Software bugs Machine code Instruction set architectures Buffer overflow Address space layout randomization PaX JMP NOP Pointer Computer architecture Computing X86 instructions
897	Ministry of Education Transfer Payments and Financial Reporting Branch st 21 Floor, Mowat Block Add to Reading List Source URL: faab.edu.gov.on.ca Language: English - Date: 2006-05-12 09:39:00 Central processing unit Processor register Instruction set architectures
898	Microsoft Word - Data Dictionary for NSP3 Data Add to Reading List Source URL: www.huduser.org Language: English - Date: 2010-10-22 18:15:18 United States housing bubble Instruction set architectures Home Mortgage Disclosure Act United States federal banking legislation Unemployment Foreclosure Census DEC Alpha Statistics Economics Mortgage industry of the United States
899	Multiprecision multiplication on AVR revisited Michael Hutter · Peter Schwabe July 31, 2014 Abstract This paper presents new speed records for multiprecision multiplication on the AVR ATmega family of 8bit microcontrol Add to Reading List Source URL: eprint.iacr.org Language: English - Date: 2014-07-31 11:18:19 Multiplication Microcontrollers Central processing unit Instruction set architectures Multiplication algorithm Anatolii Alexeevitch Karatsuba Karatsuba algorithm Atmel AVR Processor register Mathematics Arithmetic Computer architecture
900	1 Three Generations of Asynchronous Microprocessors Alain J. Martin, Mika Nystr¨om, Catherine G. Wong Department of Computer Science Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2003-08-13 19:45:22 Electrical circuits Instruction set architectures MIPS architecture Asynchronous circuit R4000 Quasi Delay Insensitive R4600 Alpha 21064 Central processing unit Computer architecture Electronic engineering Computer hardware

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